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Test the Transceiver Performance Using Pre-Defined Designs
transceiver locks to the incoming data, the RX CRU rx_freqlocked Lock
to : field displays Data indicating that the receiving PLL has recovered the
clock from the incoming data.
Link Control Settings
The bottom center of the control panel window provides the Link
Control settings. The Link Control settings include the following options:
■
■
■
■
■
■
Using SMA Clock —When the Using SMA Clock field is selected,
the serial data rate is shown as a multiplication factor of the clock
frequency for all channels. The multiplication factor is based on the
channel width used in the test design. When the external clock is
used to run the transceiver, the P and N differential outputs of the
clock source should be connected to SMA connectors J5 and J6
respectively and switch S9 should be set to the SMA position.
What statistic to display? —This list displays the bit error rate,
number of bits received, number of errors received, and error rate
slope. The error rate slope provides an approximate indication of the
increasing and decreasing trend of the number of errors received.
Inject Error —This button injects errors in the channels. Every time
this button is asserted, a one bit error is introduced.
Data Pat Rst —Reset for the data pattern generators and checkers.
Data Rate —Based on the selected test design, the Data Rate box
displays the serial data rate of the transceiver channels.
GXB Encoding —The GXB Encoding box displays whether the data
sent by the test design is 8B/10B encoded.
Data Chk Status —Before transmitting the data patterns, the pattern
generators transmit a pre-defined header byte to enable the error
checkers. Upon receiving the pre-defined header byte, the error checker
monitors for errors in the received pattern. The Data Chk Status box
displays the following:
●
●
Sync’d status displayed in green indicates that the error checker
has received the pre-defined header byte and no errors are
detected.
Unsync’d status displayed in gray indicates that the error
checker has not received the pre-defined header byte. When this
situation occurs, you should ensure that the transmitter of the
channel showing Unsync’d is connected to the receiver channel
by external cable or by internal serial loopback. Still, when
2–16 Getting Started User Guide
Altera Corporation
Transceiver Signal Integrity Development Kit, Stratix II GX Edition
June 2006
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